PhD-Optimization of Micropillar Microfabrication Process for Fan-Out Wafer Level Packaging

id="offer-description" class="ecl-u-type-heading-2 ecl-u-mt-none ecl-u-mb-l">Offer Description Context: Advanced packaging technologies are essential for the evolution of microelectronics, enhancing performance through heterogeneous integration. Traditional methods struggle to meet the demands of high-performance computing, AI, aerospace, and defense. With the growing demand for multi-chip heterogenous integration using advanced FOWLP, there is significant interest in reducing the die-to-wafer interconnect pitch, as a smaller pitch enables simpler, more efficient circuits, resulting in lower power consumption and reduced design complexity. However, reducing the bump size to such a pitch introduces new challenges, particularly in terms of thermomechanical strength, resistance to electromigration, and warpage control. In addition, a major challenge in multi-chip FOWLP processes is achieving high-accuracy die placement during the flip-chip die-to-wafer (D2W) bonding process, as the positions of the micro-bumps (contact-pad) must align with the redistribution layer (RDL) masks. This thesis project aims to develop high-density vertical interconnections (< 30 μm pitch) compatible with a manufacturing D2W assembly environment for heterogeneous multichip integration. Topic: This thesis aims to engineer an advanced manufacturing process for creating fine-pitch, ductile heterogeneous solder micro-bumps, critical for flip-chip D2W assembly of active chips onto reconstructed wafers. The