Post-Doctoral Research Visit F/M Post-Doctoral Research Visit F/M - LLM, autotuning, SIMD - Joint IFPEN-Inria laboratory

id="offer-description" class="ecl-u-type-heading-2 ecl-u-mt-none ecl-u-mb-l">Offer Description Numerical simulation is a strategic tool, useful for accelerating discoveries and innovations. The performance of simulators are thus of paramount importance to enable scalable high temporal resolution studies and to consider a wider range of scientific hypotheses. High Performance Computing (HPC) systems offer parallelism in multiple ways to address this computational demand: they are composed of many nodes, each with multiple cores (which may be heterogeneous or rely on Simultaneous Multi-Threading, SMT), using Single Instruction Multiple Data (SIMD) vectorization, with Graphics Processing Unit (GPU) accelerators. Both the software and hardware stacks present an array of diverse levers (tunable, such as process parallelism, SIMD, thread and data mapping for Non-Uniform Memory Access, burst buffers, frequency, or prefetching) to align applications (without code changes) with the unique characteristics of the hardware they run on. Interestingly, the recent code transformation capabilities of LLMs, assuming they can be verified, further offer a lever to tune applications through prompting describing code changes to apply. While tuning these levers provides gains, co-optimizing them together is key as their behaviors can synergize: thread and data mapping co-optimization is more efficient than a greedy approach, where threads and data are optimized in order (up to 1.7x speedup for use