(MSc/PhD)-FeFET-based in-memory computing for low-power edge artificial intelligence

id="offer-description" class="ecl-u-type-heading-2 ecl-u-mt-none ecl-u-mb-l">Offer Description Context. Edge AI requires low-power architectures that process data locally. Conventional systems are limited by repeated transfers between memory and computing units. Research project The project aims to design, model, simulate, and characterize a FeFET-array in-memory computing architecture to accelerate convolutional neural network (CNN) inference for edge-AI applications. The devices and circuits will be fabricated by a foundry through an MPW program, then experimentally validated and compared with a digital reference. Proposed activities. Define the CNN hardware architecture, weight representation, and layer mapping onto FeFET arrays. Develop SPICE or Verilog-A FeFET models including analog programming and main non-idealities. Design memory cells, MAC arrays, and peripheral circuits for programming, readout, and accumulation. Simulate accuracy, energy, latency, throughput, and silicon area while considering variability, noise, retention, and endurance. Prepare MPW test blocks, develop the measurement setup, and characterize fabricated circuits. Run a CNN using measured data and compare performance with simulations and a digital reference. Expected outcomes. FeFET in-memory computing architecture designed, simulated, and validated for CNN execution. Device and circuit models calibrated using experimental measurements. MPW-fabricated integrated circuit, characterization setup, an