RTL Design Engineer, Networking / NoC

OpenAI's Hardware organization develops AI-native silicon and system-level solutions for advanced AI workloads. We're looking for an RTL Design Engineer to help design and develop next-generation AI accelerator silicon. In this role, you'll work across architecture, microarchitecture, and RTL implementation, translating complex system and performance requirements into efficient, scalable hardware designs. You'll collaborate closely with silicon architects, hardware and software engineers, verification, and physical design teams to co-design hardware solutions optimized for demanding AI workloads. Responsibilities: Design and implement high-performance RTL for next-generation AI accelerator silicon Collaborate with architecture and software teams to translate system-level requirements into efficient hardware microarchitectures Drive hardware/software co-design efforts to optimize performance, power, area, and scalability for AI workloads Develop and optimize RTL for complex datapaths, control logic, interconnects, and other critical silicon subsystems Evaluate architectural and microarchitectural tradeoffs across bandwidth, latency, throughput, and resource utilization Partner with design verification and formal verification teams to ensure functional correctness Work closely with physical design teams to optimize RTL for synthesis, timing closure, power, and area Contribute to architecture reviews, design specifications, and cross-functional discussions to influence future silicon designs Support block-level and SoC-level integration, debugging, and performance optimization Requirements: Strong hands-on experience with ASIC RTL design and microarchitecture development using SystemVerilog or Verilog Experience designing and implementing complex digital hardware blocks Understand hardware architecture and microarchitecture tradeoffs Experience collaborating across architecture, software, verification, and physical design teams Ability to reason about complex hardware systems and translate architectural requirements into efficient RTL implementations Experience with synthesis, timing closure, and physical implementation considerations Experience with Network-on-Chip (NoC), networking, interconnect fabrics, packet-based architectures, or high-bandwidth data movement systems Benefits: Competitive salary ($287K - $485K) Opportunities for professional growth and development Collaborative and dynamic work environment Job Data by YubHub .