ASIC Physical Design, Principal Engineer

Synopsys · Sunnyvale, California · $197800-$296700 Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. You have spent over a decade taking SerDes and high-speed interface IP from RTL to silicon, and you know that the hardest problems are not the ones in the datasheet. They are the ones that show up at 16nm when your timing closure strategy collides with a power domain you did not account for, or when a customer integration uncovers an assumption you made six months ago that no longer holds. You are the engineer who catches those problems early, not because you are paranoid, but because you have seen what happens when they slip through. At Synopsys, you will work on 112G and 224G PAM4/6 SerDes IP at nodes where every decision about placement, clocking, and power matters. The team is technical, the problems are real, and what you build will ship in products that move data at scale. What You'll Be Doing Own physical integration for advanced SerDes IP from floorplanning through GDSII, including timing closure, power optimization, and signoff at 16nm and below Drive RTL-to-GDSII flows for 56G, 112G, and 224G PAM4/6 SerDes across FinFET nodes, working closely with front-end, analog, and CAD teams to resolve integration challenges Develop and validate timing constraints, clock architectures, and low-power design techniques that meet customer PPA targets and enable first-pass silicon success Lead customer engagements on physical integration topics, including SOC-level integration planning, constraint delivery, and tapeout support Build and improve design methodologies, automation scripts (Perl, Tcl, Python), and flows that reduce customer effort and improve delivery predictability Debug and resolve complex analog-digital interface issues in collaboration with analog design and verification teams Mentor engineers across the team on physical design best practices, timing closure strategies, and advanced node challenges The Impact You Will Have Your physical integration work will enable high-speed SerDes IP to meet aggressive PPA targets in customer SoCs across data center, AI, and networking applications You will reduce customer integration effort and risk by delivering robust constraints, proven flows, and clear guidance that accelerates their tapeout schedules Your methodology improvements and automation will make the entire team faster and more consistent, reducing rework and late-stage surprises You will help shape the technical direction of future SerDes products by identifying architectural and flow improvements based on real tapeout learnings Your customer interactions will surface integration challenges early, allowing the team to address them in IP rather than forcing workarounds downstream You will build technical depth across the team by sharing what you have learned from advanced node tapeouts and complex mixed-signal integration Your work will directly contribute to the success of Synopsys SerDes IP in the most demanding, highest-performance applications in the industry What You'll Need MSEE with 10+ years or BSEE with 12+ years of digital or physical design experience, with recent contributions to project tapeouts Deep hands-on experience with the full RTL-to-GDSII flow, including chip-level integration, timing closure, and physical signoff Proven experience with advanced FinFET nodes (TSMC 16nm or below), including low-power design techniques and process-specific challenges Strong understanding of timing constraint development, clock architecture, and design techniques required to meet power and area targets Experience leading technical initiatives or projects, with a track record of driving decis