DDR I/O Analog and Mixed-Signal Design Intern

Synopsys · Yerevan · onsite Our internship programs offer real-world projects, hands-on experience, and opportunities to collaborate with passionate teams globally. You’ll join a team focused on DDR/LPDDR PHY and high-speed I/O circuit design, working alongside experienced analog and mixed-signal circuit designers. What You’ll Be Doing Assist with transistor-level design and simulation of DDR I/O circuits. Analyze timing, power, signal integrity, and PVT variations. Contribute to the design and functional verification of TX, RX, clocking, calibration, and power-delivery circuits. Develop simulation testbenches and automate result analysis. Debug schematic, layout, and post-layout simulation results. Document technical findings and present results to the design team. Gain hands-on experience with production DDR/LPDDR PHY development and advanced semiconductor design methodologies. The Impact You Will Have Contribute to the development and characterization of high-performance DDR/LPDDR PHY circuits. Support analysis and verification activities that help ensure circuit performance across different operating conditions. Help improve simulation and analysis efficiency through testbench development and automation. Contribute to identifying and resolving circuit-level issues through schematic, layout, and post-layout analysis. Build practical analog and mixed-signal IC design experience while contributing to real-world semiconductor development. What You’ll Need Currently pursuing a BS or MS in Electrical Engineering or a related discipline. Coursework in analog/mixed-signal IC design, CMOS circuits, or VLSI. Understanding of MOS device operation and basic circuit analysis. Familiarity with SPICE simulation. Scripting experience with Python, Perl, Tcl, or Shell. Strong analytical, debugging, and communication skills. Knowledge of DDR, LPDDR, or other high-speed interfaces is a plus. Experience with Cadence or Synopsys custom-design tools is a plus. Familiarity with signal integrity, clocking circuits, statistical analysis, or post-layout verification is a plus. Exposure to advanced-node CMOS design is a plus. Good written and spoken English skills, including the ability to read and write technical documentation